pvperfsolar performance modeling

Reference / DC ohmic wiring

Model option

Load ratio

The design fraction scaled by the load ratio

Inputs used: Loss fraction at STC (DC circuit), Global wiring resistance

Method

The loss at every timestep is the design fraction times the array power times the ratio of the array power to its nameplate (1), so the loss fraction grows in proportion to the load and equals the design fraction at nameplate power. No fixed resistance is derived. For the operating-point search, each timestep uses the resistance that gives this loss at the maximum-power current (2).

The math

  1. Wiring loss
  2. Resistance of the operating-point search
Li=fw Pi PiPnom,dc(1)L_i = f_w\,P_i\,\frac{P_i}{P_{nom,dc}} \tag{1} Rw,i=LiImpp,i2(2)R_{w,i} = \frac{L_i}{I_{mpp,i}^2} \tag{2}

where

Symbol Meaning Unit
LiL_i the wiring loss at timestep ii W
fwf_w the design loss fraction —
PiP_i the array DC power after the flat derates at timestep ii W
Pnom,dcP_{nom,dc} the array DC nameplate W
Rw,iR_{w,i} the equivalent wiring resistance at timestep ii Ω
Impp,iI_{mpp,i} the array current at maximum power at timestep ii A

API

dc_losses.ohmic_model = load_ratio

Symbols follow the symbol registry.