Model option
Load ratio
The design fraction scaled by the load ratio
Inputs used: Loss fraction at STC (DC circuit), Global wiring resistance
Method
The loss at every timestep is the design fraction times the array power times the ratio of the array power to its nameplate (1), so the loss fraction grows in proportion to the load and equals the design fraction at nameplate power. No fixed resistance is derived. For the operating-point search, each timestep uses the resistance that gives this loss at the maximum-power current (2).
The math
- Wiring loss
- Resistance of the operating-point search
where
| Symbol | Meaning | Unit |
|---|---|---|
| the wiring loss at timestep | W | |
| the design loss fraction | — | |
| the array DC power after the flat derates at timestep | W | |
| the array DC nameplate | W | |
| the equivalent wiring resistance at timestep | Ω | |
| the array current at maximum power at timestep | A |
API
dc_losses.ohmic_model = load_ratio
Symbols follow the symbol registry.