Model step
DC ohmic wiring
Resistive loss in DC wiring
Inputs used: Loss fraction at STC (DC circuit), Global wiring resistance
What it is
The resistance of the DC cables between the modules and the inverter turns part of the power into heat. The design gives the loss at standard test conditions. The options set how that loss varies with the load.
Options
- I²R on the MPP current: resistance times the square of the array current
- Load ratio: the design fraction scaled by the load ratio
- Flat fraction: the design fraction of the array power at every timestep
References
- PVsyst 8 help, Array ohmic wiring loss
API
dc_losses.ohmic_model = ohmic_i2r | load_ratio | flat